You can find all the required documentation on Github. We also arrange open and on-site courses all over the world on request. For already scheduled courses see here.
Documentation (Github)UVVM is an Open Source VHDL testbench infrastructure, Architecture, Library and Methodology for making better VHDL tesbenches.
Known bugs:
Modelsim/Questa2019.2 does not work with UVVM. Do not use this version. Previous and laterversions work fine.