• State-of-the-art Verification Methodology
• Open Source library
• Testbench kickstart for any project
• Great TB overview and readability
• Modular, reusable and extendable
• Easy to maintain
• Vital for FPGA quality
• Significantly improves efficiency
VVC+BFM randomisation updates
Avalon Stream: +Random Valid and Ready
Specification Coverage: Major updates
Various doc from pdf to RST/html
Completion Detection
Detection of unwanted transactions
Various minor Improvements and Fixes
Various minor Improvements and Fixes
HDLRegression released
Functional Coverage: Major updates + Demo
Started conversion of Documentation from PDF to RST/html
Enhanced Randomisation
Optimised Randomisation
Functional Coverage
Wishbone
AXI Stream: +Random Valid and Ready
AXI4
GPIO: new commands
Maintenance Testbenches and MS-Wordsources for PDFs testing the brake.
Ethernet VVC
Specification Coverage
Avalon Stream
GMII
RGMII
Activity watchdog
Built-in Scoreboards
VVC Transaction Info
Error Injection VIP
More new UVVM functionality: Simulation Completion Detection
A new improvement to come early out of the current ESA UVVM project is: Completion Detection.
This brand new functionality will allow your testbench to detect that your simulation is finished – or to wait for that to happen.
UVVM has had functional coverage and specification coverage (aka requirements tracking) for several years, and that is great in many ways.
They do however not necessarily say anything about whether there are commands pending in your verification components or data pending in your scoreboards.
The broadcast of 'await_completion()' has been available for many years, but for Scoreboards, the user has had to check every single one for pending expected data.
With the new completion detection mechanism you can check all Scoreboards simultaneously using one single command – and you may even combine this with waiting for all VVCs (Verification components) to complete.
This makes it both easier and safer to make good test cases.We expect this new functionality to be published in June - together with the new functionality on ' Detection of unexpected interface activity'
New UVVM functionality: Detection of unexpected interface activity
One of the first improvements to come out of the new ESA UVVM project is detection of unexpected activity on a DUT interface. UVVM has provided open source BFMs (Bus Functional Models) and VVCs (VHDL Verification Components) for lots of interfaces - like AXI, AXI-stream, AXI-light, SPI, UART, SBI, Ethernet, GMII, GPIO, Avalon MM, Avalon stream, etc. - for a long time. These have provided excellent access mechanisms for transaction modelling, but also various support for protocol checking. Normal BFMs and VVCs have the limitation though, that they only initiate a transaction or wait for one to occurr. They do not check whether the DUT is only transmitting data when expected.
UVVM now introduces detection of any unwanted or unexpected transactions from the DUT. In fact, UVVM will now detect any unwanted or unexpected activity on a given interface. This new checker may of course be turned on and off from the test sequencer.
We expect this new functionality to be published in June.
New ESA project
ESA (the European Space Agency) has just started a new ESA-UVVM project to extend the functionality of this great tool even further.
More info to come soon.
Regression testing is re-running tests to check that previously developed and tested code still performs after a change in the code. In FPGA development we often write many testcases to check the functional correctness of our design, and testcases can be run many times during the development process.
We know that proper verification can be time-consuming and that often more than half the project development time is spent on verification including writing testcases, structuring, debugging, and keeping track of testcase results and requirements. Setting up the simulation of the complete test suite with proper testcase traceability can, depending on the size and complexity of the design under test, be tedious and time-consuming.With regression testing we test frequently, and we often write tests for small modules - almost like unit tests, test large modules and top-level designs. Complex designs can have numerous testcases, thus automating the verification flow is a big advantage and sometimes unavoidable.
HDLRegression is a test automation regression system for structuring the test flow and simulating testcases, all controlled from a single test script written in Python 3. With HDLRegression the verification engineer can easily setup the complete verification flow and quickly start simulating and check the functional correctness of the design. Setting up a test script can be done in minutes, and with the power of the Python language we can create advanced and effective test scripts to set up testbench generics and control testcases.
Some of the benefits of using HDLRegression to control the test suite:
- Easy to setup with new and existing projects through provided template files.
- Simple simulation control from command line
- Interactive recompilation and testcase control from Questa and Modelsim GUI - and easy to extend with more simulators.
- Continous testcase simulation status
- Verbosity control
- Ensure all testcases are run
- Use with any verification framework
- Veriolog and VHDL support
- Automatic compilation and re-running of testcases
- Run on CI servers
https://github.com/HDLUtils/hdlregression
UVVM is now an IEEE Standards Association Open Source project.
In fact, UVVM has been an IEEE open source project for some time already, but we wanted to publish this at the same time as we publish that a 'UVVM working/advisory group' will be established.
The group will be following the policies of the IEEE standards Association and cooperate to make UVVM the best possible verification library and methodology for VHDL designers in order to speed up FPGA and ASIC development and improve product quality.
The group will consist of users with a strong interest in UVVM, and a passion to achieve the above goals for the VHDL community.
UVVM on IEEE is a logical follow-up on one of the main ideas of UVVM – to standardise the VVC architectures and interfaces to allow verification models from any UVVM user to work inside any UVVM based testbench.
Establishing such a group is a logical follow-up for a 100% open source verification methodology and library – like UVVM. We are now preparing for this and will provide more information soon.
UVVM is an open source verification tool developed and sponsored by leading industry actors.
Known bugs:
Modelsim/Questa2019.2 does not work with UVVM. Do not use this version. Previous and later versions work fine.
Modelsim SE-64 10.1c also has some issues.
Visit the UVVM discussion forum for latest information, tips and questions
