• Open Source library
• Testbench kickstart
• Great overview and readability
• Efficient and easy to maintain
• Modular, reusable and extendable
• Vital for FPGA development quality
• Modern verification methodology
Maintenance Testbenches and MS-Wordsources for PDFs testing the brake.
VVC Transaction Info
Error Injection VIP
Regression testing is re-running tests to check that previously developed and tested code still performs after a change in the code. In FPGA development we often write many testcases to check the functional correctness of our design, and testcases can be run many times during the development process.
We know that proper verification can be time-consuming and that often more than half the project development time is spent on verification including writing testcases, structuring, debugging, and keeping track of testcase results and requirements. Setting up the simulation of the complete test suite with proper testcase traceability can, depending on the size and complexity of the design under test, be tedious and time-consuming.With regression testing we test frequently, and we often write tests for small modules - almost like unit tests, test large modules and top-level designs. Complex designs can have numerous testcases, thus automating the verification flow is a big advantage and sometimes unavoidable.
HDLRegression is a test automation regression system for structuring the test flow and simulating testcases, all controlled from a single test script written in Python 3. With HDLRegression the verification engineer can easily setup the complete verification flow and quickly start simulating and check the functional correctness of the design. Setting up a test script can be done in minutes, and with the power of the Python language we can create advanced and effective test scripts to set up testbench generics and control testcases.
Some of the benefits of using HDLRegression to control the test suite:
- Easy to setup with new and existing projects through provided template files.
- Simple simulation control from command line
- Interactive recompilation and testcase control from Questa and Modelsim GUI - and easy to extend with more simulators.
- Continous testcase simulation status
- Verbosity control
- Ensure all testcases are run
- Use with any verification framework
- Veriolog and VHDL support
- Automatic compilation and re-running of testcases
- Run on CI servers
UVVM is now an IEEE Standards Association Open Source project.
In fact, UVVM has been an IEEE open source project for some time already, but we wanted to publish this at the same time as we publish that a 'UVVM working/advisory group' will be established.
The group will be following the policies of the IEEE standards Association and cooperate to make UVVM the best possible verification library and methodology for VHDL designers in order to speed up FPGA and ASIC development and improve product quality.
The group will consist of users with a strong interest in UVVM, and a passion to achieve the above goals for the VHDL community.
UVVM on IEEE is a logical follow-up on one of the main ideas of UVVM – to standardise the VVC architectures and interfaces to allow verification models from any UVVM user to work inside any UVVM based testbench.
Establishing such a group is a logical follow-up for a 100% open source verification methodology and library – like UVVM. We are now preparing for this and will provide more information soon.
UVVM is an open source verification tool developed and sponsored by leading industry actors.
Modelsim/Questa2019.2 does not work with UVVM. Do not use this version. Previous and later versions work fine.
Modelsim SE-64 10.1c also has some issues.
Visit the UVVM discussion forum for latest information, tips and questions