UVVM is an Open Source VHDL testbench infrastructure
Architecture, Library and Methodology for making better VHDL tesbenches. UVVM is used world wide to speed up verification and improve the overall FPGA design quality. Applicable for both FPGAs and ASICs.
There are additional support libraries/components - like BFMs (Bus Functional Models) and VVCs (VHDL Verification Components). Some free and Open Source componets are included in the UVVM VVC framework download file (ZIP).
Quick-References of various components and libraries (also in ZIP) are listed in each VIP overview.
• Avalon MM
• Avalon ST
• Clock Generator
• Error Injection
• Specification Coverage