UVVM is an Open Source VHDL testbench infrastructure

Architecture, Library and Methodology for making better VHDL tesbenches. UVVM is used world wide to speed up verification and improve the overall FPGA design quality. Applicable for both FPGAs and ASICs.

Main features

Advanced Randomization

Functional
Coverage

Monitors

Error Injection

Scoreboards

Transactions

Verbosity control

Specification Coverage

Checkers

Alert handling

Logging

Specification Coverage

Specification Coverage

Specification Coverage

Utility Library - Verification entry-level

Utility Library
  • Easy and understandable command syntax
  • Basic logging and alert handling
  • Basic value checkers and signal value expectors
  • Great overview even for complex designs
  • May combine with randomization and functional coverage
  • Compliance with regression test tools like Jenkins

Utility Library - Verification entry-level

VVC Framework
  • Structured, LEGO-like test harness
  • Allow simultaneous, multiple interface stimuli and checking
  • Efficient reuse of Verification Components
  • Semi automated generation of new VVCs
  • Simple handling of split transactions (e.g. pipeline access)
  • Simple encapsulation for a complete interface or protocol
  • Allows VVCs instantiation even in the Design it self
  • Logging and alert handling with verbosity control
  • Quick References for UVVM and all included BFMs/VVCs
VHDL Verification Component

All VVCs share the same straight forward, self-explanatory and structured micro architecture, making it easy to develop new VVCs from an automatically generated template. It consists of three main parts: A Command Interpreter, a Command Queue and a Command Executor which will handle the interface protocol.

Supported simulators
  • Aldec Active-HDL
  • Aldec Riviera Pro
  • Mentor Graphics Modelsim
  • Mentor Graphics Questa
  • Vivado: Awaiting proper VHDL 2008 support
  • GHDL

Verification Components

There are additional support libraries/components - like BFMs (Bus Functional Models) and VVCs (VHDL Verification Components). Some free and Open Source componets are included in the UVVM VVC framework download file (ZIP).

Quick-References of various components and libraries (also in ZIP) are listed in each VIP overview.

Avalon MM
Avalon ST
AXI
AXI-Lite
AXI-Stream
Clock Generator
Error Injection
Ethernet
GMII
GPIO
HVVC
I2C
RGMII
SBI
Scoreboard
Specification Coverage
SPI
UART
Wishbone